1. Technical Field
The present invention relates to a SONOS memory device having a curved surface and a method for fabricating the same, and more particularly to a SONOS memory device, of which multi-dielectric layers (for example, ONO layers: Oxide/Nitride/Oxide layers) have a cylindrical surface, and a method for fabricating the same.
2. Description of Related Art
Currently, a SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) memory device has been paid attention to as the next generation of memory device. Especially, a SONOS memory device is considered to be a potent flash memory cell for the next generation because it can take advantage of a large amount of deep level traps, which exist in a nitride layer among multi-dielectric layers.
However, a conventional SONOS memory device has been fabricated in a planar NMOS type, as shown in FIG. 1. It has an energy band diagram like FIG. 2. The average thermal energy of electrons is only 0.025 eV at room temperature (300K). Therefore, to program a SONOS memory device, it is necessary to find special methods for electrons of a substrate 10 to get into a nitride layer 34 of multi-dielectric layers 30 beyond the energy barrier (3.1 eV) of a tunneling oxide 32. One method is CHE (Channel Hot-Electron) injection in which electrons in a channel can be injected by accelerating them to overcome the energy barrier (3.1 eV) of a tunneling oxide 32. The other method is F-N tunneling (Fowler-Nordheim tunneling).
In F-N tunneling, as shown in FIG. 3, an energy band diagram would be changed by applying voltage to both ends of a substrate 10 and a control gate 40 (especially, high voltage to a control gate) which heightens the possibility that electrons from the conduction band (Ec) of a substrate will penetrate a tunneling oxide 32, which becomes thin on the energy band diagram, and enter a nitride layer 34.
As shown in Equation 1, a tunneling current J is proportional to a probability Tt that electrons of a conduction band of a substrate will penetrate a barrier, such as a tunneling oxide. Tt is exponentially proportional in inverse to the thickness x1 of the barrier, which electrons of a conduction band (Ec) of a substrate see, as shown in Equation 2 x1 is inversely proportional to the electric field (∈OX) formed across the barrier (a tunneling oxide) as shown in Equation 3.
                    J        =                                            4              ⁢              π              ⁢                                                          ⁢              qm                                      h              3                                ⁢                                    ∫              0                              E                F                                      ⁢                                          ⅆ                E                            ⁢                                                ∫                  0                  E                                ⁢                                                      T                    t                                    ⁢                                      ⅆ                                          E                      t                                                                                                                              <                  Equation          ⁢                                          ⁢          1                >                                          T          t                =                  exp          ⁡                      [                                          -                2                            ⁢                                                ∫                  0                                      x                    1                                                  ⁢                                                                            k                      OX                                        ⁡                                          (                      x                      )                                                        ⁢                                      ⅆ                    x                                                                        ]                                              <                  Equation          ⁢                                          ⁢          2                >            where kOX indicates a wave vector of tunneling electrons.χ1=(ΦB+EF−E)/q∈OX  <Equation 3>
In F-N tunneling a higher voltage is applied to a control gate compared to a substrate, which changes the energy band as shown in FIG. 3. As the conduction band of the tunneling oxide slants downward, the thickness of a barrier, which electrons of a conduction band of a substrate see, becomes thinner than before. Therefore, the possibility that electrons of a conduction band of a substrate will penetrate a tunneling oxide becomes greater, and it makes quantum mechanic tunneling current flow. As a result, F-N tunneling enables injection of electrons into a nitride layer of multi-dielectric layers for programming.
Meanwhile, electrons injected into a nitride layer of multi-dielectric layers should be emitted or eliminated for erasing a SONOS memory device, and the F-N tunneling has been mainly used for erasing a SONOS memory device. Contrary to that described above for programming, when a lower voltage to a control gate compared to a substrate is applied, it leads an energy band to be changed as shown in FIG. 4. A valence band of tunneling oxide slants upwardly, and finally, the thickness of a barrier, which holes in the valence band (Ev) of a substrate see, becomes thinner than before. Therefore, the possibility that holes of a valence band of a substrate will penetrate a tunneling oxide becomes greater, and it makes quantum mechanic tunneling current flow in the opposite direction as above. As a result, F-N tunneling enables injection of holes into a nitride layer of multi-dielectric layers for erasing.
However, in a conventional planar type SONOS memory device as shown in FIG. 1, F-N tunneling for erasing has the problem that electrons, that penetrated a blocking oxide 36 from a control gate 40 and entered a nitride layer 34 of multi-dielectric layers by back-tunneling, make the speed of an erase operation slower, and recovery of a threshold voltage to the original state ceases at a certain level. Namely, there is the possibility that electrons of a conduction band of poly-silicon, a control gate, also will penetrate a thin barrier (blocking oxide) and enter a nitride layer of multi-dielectric layers, and it takes a long time to remove the electrons, and in addition, removing electrons has limits.
Therefore, the incomplete erase problems should be overcome to commercialize a SONOS device as a memory device.
One method to solve the erase problem is hot-hole injection. According to this method, in a NMOS structure as shown in FIG. 5, applying a high negative voltage between a source or a drain and a body with reverse bias brings about a result that a N+ region of a source or a drain under a gate becomes inversed at the surface, and as a result, holes are generated. Then, the electric field is high at the partially formed N+-P+ junction, and band-to-band tunneling can occur. After that, holes escaping toward a channel become more accelerated by a voltage applied between a source or a drain and a body, and among holes, hot holes with enough momentum can be injected easily into a nitride layer with the help of a gate voltage. Despite their heavy mass and the tunneling barrier, such hot holes have much larger energy than F-N tunneled holes do, and therefore, can be injected effectively into a nitride layer.
However, an erase of a memory by hot hole injection should be accompanied by setting a gate voltage and a body voltage as well as by setting a source bias and a drain bias at a predetermined value, respectively. But, there is a problem that such a method cannot be applied in a NAND type flash memory array. When a high negative voltage is applied to a gate for erase by the hot hole injection in a conventional NMOS type memory device, the channel turns off due to an accumulation mode, and a voltage supplied from a bit line cannot be effectively delivered to a source and a drain of each memory device, which are connected with each other in series.
Therefore, in a NAND type flash memory, using both program and erase by F-N tunneling, the erase speed problem by back-tunneling effect has been the main reason to delay the commercialization of a SONOS memory.
Until now, there have been various trials to improve the erase speed problem not by the hot-hole injection but by the F-N tunneling.
Among them, Reisinger et al., used a poly-silicon doped with P+ rather than N+ for a gate of a SONOS memory device, and this raised a tunneling barrier between a gate and a nitride layer to lessen the back-tunneling effect (Dig. Symp. VLSI Tech., 1997, pp. 113-114). But when a high negative voltage is applied to a gate (word line), electrons of a valance band at a gate tunnel to the nitride layer and there are still some limits for improving the erase speed.
Another method to improve the erase speed is to replace a blocking oxide 36 in FIG. 1 with high-k dielectrics (for instance, Al2O3) to increase the capacitance of a blocking layer (Ext. Abst. Int'l Conf. Solid State Dev. Materials, 2002, pp. 162-163), or to use metal TaN, instead of poly-silicon for a gate of a SONOS memory device (Tech. Dig. Int'l Electron Dev. Meet., 2003, pp. 613-616). But these methods still have problems in that the use of a high-k material or a metal gate severely diminishes the silicon CMOS technology compatibility, and it cannot make the best use of the advantages of a SONOS.